1. Field of the Invention
The present invention generally relates to a dependent synchronous apparatus and an SDH (synchronous digital hierarchy) apparatus having the dependent synchronous apparatus, and particularly relates to a dependent synchronous apparatus capable of identifying a direction of a timing dependency and an SDH apparatus having such a dependent synchronous apparatus.
2. Description of the Related Art
SDH networks employ a dependent-synchronization scheme. SDH networks are a synchronous network, and, thus, it is vital to maintain synchronization at all times. To this end, various measures are taken in order to avoid severing of a synchronous network caused by master-clock failures or failures of communication lines for transferring timing signals.
FIG. 1 is an illustrative drawing showing a schematic configuration of an SDH network.
The network of FIG. 1 includes a primary master clock 19 and a secondary master clock 20. More than one master clock is provided in order to insure redundancy.
The network also includes network elements NE1 through NE4. A network element that receives an output of a master clock directly therefrom is referred to as a gateway network element (GNE) of a synchronous system. In FIG. 1, the network element NE1 and the network element NE2 are gateway network elements.
Each network element is provided with a function to select a timing source so that the network element operates in synchronism with the selected timing source. The timing-source selection function of each network element NE usually allows a plurality of timing sources to be selected and given priority. Prioritized timing sources are monitored all the time with regard to quality thereof, and a timing source having the highest quality is selected for use. If more than one timing source exhibits the same quality, a timing source having the highest priority is selected for use. If the timing source currently in use is degraded in terms of quality thereof, a timing source having the next highest quality automatically replaces the current timing source.
Quality of timing sources is transferred via an overhead in the case of an STM-n (synchronous transfer mode-n).
FIG. 2 is an illustrative drawing showing a format of an STM-1 overhead.
An STM-1 overhead is comprised of 3 rows of RSOH (regenerator section over head), a pointer row, and 6 rows of MSOH (multiplex section over head). RSOH is terminated at each transit apparatus, and RSOH is terminated at a transit apparatus connected to a terminal. A pointer in the pointer row indicates a start position of a signal in the payload.
FIG. 3 is an illustrative drawing showing an S1 byte of an SOH (section over head). Here, the S1 byte is a Z1#1 byte of an old system.
As shown in FIG. 3, quality of a timing source is transferred by using SSMB, which is inserted into four lower bits of the S1 byte.
As will be described later, SSMB is defined by binary codes shown in ITU-T, G.708. These binary codes define quality of a SDH timing with respect to each combination of the four bits of SSMB. For example, xe2x80x9c0010(02h)xe2x80x9d indicates that a timing source has a quality equivalent to that of xe2x80x9cG.811xe2x80x9d (a primary timing source using a cesium atomic oscillator), and xe2x80x9c1111xe2x80x9d indicates that the timing source should not be used for synchronization.
The network element NE1 of FIG. 1 is a gateway network element of the synchronous system, and, thus, selects an external clock input A from the primary master clock 19 as a timing source of a first priority. When quality of the external clock input A from the primary master clock 19 degrades, a transfer line G is selected as a timing source of a second priority since a clock in synchronism with the secondary master clock 20 is now necessary.
The network element NE2 needs a clock from the network element NE1 such that the clock is in synchronism with the primary master clock 19, and, thus, selects a transfer line B as a timing source of a first priority. When quality of the transfer line B degrades, a transfer line F is selected as a timing source of a second priority since a clock in synchronism with the secondary master clock 20 is now necessary.
The network element NE3 needs a clock from the network element NE2 such that the clock is in synchronism with the primary master clock 19, and, thus, selects a transfer line C as a timing source of a first priority. When quality of the transfer line C degrades, a transfer line E is selected as a timing source of a second priority since a clock in synchronism with the secondary master clock 20 is now necessary.
The network element NE4 needs a clock from the network element NE3 such that the clock is in synchronism with the primary master clock 19, and, thus, selects a transfer line D as a timing source of a first priority. When quality of the transfer line D degrades, an external clock input H from the secondary master clock 20 is selected as a timing source of a second priority since a clock in synchronism with the secondary master clock 20 is now necessary.
A synchronous network is established in such a manner as described above.
In FIG. 1, the primary master clock 19 may be comprised of a cesium atomic oscillator, and the secondary master clock 20 may be comprised of a rubidium atomic oscillator. A description of such a configuration will be given in the following.
The network element NE1 transmits an SSMB code xe2x80x9c02hxe2x80x9d to the next network element NE2 as an S1 byte signal of MSOH via the transfer line B. Here, the SSMB code xe2x80x9c02hxe2x80x9d indicates a timing quality of the primary master clock 19 that is connected to the network element NE1 and comprised of a cesium atomic oscillator. By the same token, the network element NE2 transmits the SSMB code xe2x80x9c02hxe2x80x9d to the network element NE3 as a S1-byte signal of MSOH via the transfer line C. The network element NE3 transmits the SSMB code xe2x80x9c02hxe2x80x9d to the network element NE4 as a S1-byte signal of MSOH via the transfer line D. Further, an SSMB code transferred on the transfer lines E, F, and G is set to xe2x80x9c0Fhxe2x80x9d in order to prevent a synchronous loop.
FIG. 4 is an illustrative drawing showing a situation where a failure occurs in the primary master clock 19 or on the output transfer line thereof, and the external clock input A from the primary master clock 19 has a degraded quality. In such a situation, switching of a timing source is effected in each network element, so that the SDH network as a whole is synchronized with the secondary master clock 20.
When a failure occurs with respect to the external clock input A form the primary master clock 19, the network element NE1 detects the failure, and lapses in a hold-over status. The network element NE1 changes the SSMB code from xe2x80x9c02hxe2x80x9d to xe2x80x9c0BhSETS(synchronization equipment timing source)xe2x80x9d in response to the change of quality of the timing source, and sends this SSMB code to the network element NE2 via the transfer line B. The network element NE2 transmits the SSMB code xe2x80x9c0Bhxe2x80x9d to the network element NE3 via the transfer line C. By the same token, the network element NE3 transfers the SSMB code xe2x80x9c0Bhxe2x80x9d to the next network element NE4 via the transfer line D. Consequently, the entire network is put in a hold-over status originating from the network element NE1.
In such a status, the network element NE4 compares the timing quality (SSMB code xe2x80x9c0Bhxe2x80x9d) of the transfer line D having the first priority with a timing quality (SSMB code xe2x80x9c04hxe2x80x9d) of the external clock input H having the second priority and originating from the secondary master clock 20, which is comprised of a rubidium atomic oscillator. The network element NE4 selects the timing source of the second priority because of a higher quality thereof, and sends the SSMB code xe2x80x9c04hxe2x80x9d to the network element NE3 via the transfer line E. The network element NE3 attends to a similar comparison to select the timing source of the second priority, and sends the SSMB code xe2x80x9c04hxe2x80x9d to the network element NE2 via the transfer line F. By the same token, the network element NE2 also selects the timing source of the second priority, and transfers the SSMB code xe2x80x9c04hxe2x80x9d to the network element NE1 via the transfer line G. Finally, the network element NE1 selects the timing source of the second priority since this timing source has a higher timing quality than its hold-over status.
As a result, the network elements NE1 through NE4 are now synchronized with the secondary clock signal that is supplied from the secondary master clock 20. Here, an SSMB code on the transfer lines B, C, and D is set to xe2x80x9c0Fhxe2x80x9d in order to prevent a synchronous loop.
FIG. 5 is an illustrative drawing showing a situation where quality of the transfer line C degrades, and the timing source is switched in the network elements NE3 and NE4.
The network element NE3 lapses into a hold-over status, and sends the SSMB code xe2x80x9c0Bhxe2x80x9d to the network element NE4 via the transfer line D. After this, the network element NE4 compares the timing quality (SSMB code xe2x80x9c0Bhxe2x80x9d) of the transfer line D having the first priority with the timing quality (SSMB code xe2x80x9c04hxe2x80x9d) of the external clock input H having the second priority and originating from the secondary master clock 20, which is comprised of the rubidium atomic oscillator. The network element NE4 selects the timing source of the second priority because of a higher quality thereof, and sends the SSMB code xe2x80x9c04hxe2x80x9d to the network element NE3 via the transfer line E. The network element NE3 attends to a similar comparison to select the timing source of the second priority, and sends the SSMB code xe2x80x9c04hxe2x80x9d to the network element NE2 via the transfer line F. The network element NE2 compares the SSMB code of the transfer line B with the SSMB code of the transfer line F, and keeps the current timing source.
The related-art as described above provides no means for monitoring a direction of a synchronization signal, which the network elements depend on. In order to monitor such a direction, therefore, a direction of a timing source is checked with respect to each network element, and the check results are analyzed to trace the network configuration.
In recent years, SDH networks have increased their size and complexity. This is often observed, especially, when existing SDH networks are connected together, or are connected to new SDH networks to expand the size.
FIG. 6 is an illustrative drawing showing a schematic configuration of a mesh network. The mesh network is a typical example of a large-size and complex SDH network often observed these days.
In the mesh network as shown in FIG. 6, networking of main signals is complex, and, also, networking of an SDH synchronization system is equally complex. As a complexity of a network increases, an longer time is necessary for designing and implementing a network, and it is more likely to suffer erroneous connections or erroneous setting of timing sources. Further, switching of a direction of a timing dependency (i.e., switching of timing sources) may occur in a synchronous system because of degradation of synchronization signals. In a complex network environment, therefore, it is prohibitively difficult to check which network elements depend on the primary master clock.
FIG. 7 is an illustrative drawing showing three SDH networks each having its own master clock. FIG. 8 is an illustrative drawing showing a process of integrating the three SDH networks via a network element NE19 of the network Network-2. FIG. 9 is an illustrative drawing showing an integrated SDH network.
In order to integrate the three SDH networks via the network element NE19, a network element NE12 of the network Network-1 and a network element NE20 of the network Network-3 are connected to the network element NE19 of the network Network-2. This establishes connections for main signals. Beyond this, the integrated SDH network must be synchronized with a single master clock.
As can be understood from FIG. 8, almost all the network elements need to change timing-source settings in order to synchronize the entire network under the same master clock. Further, the network element NE19 must attend to highly complex connections between each network element.
Accordingly, there is a need for a dependent synchronization apparatus which can facilitate implementation of a network, can eliminate erroneous setting of timing sources, and can allow a direction of a timing dependency to be easily checked even after an automatic switching of a direction of a timing dependency.
Accordingly, it is a general object of the present invention to provide a dependent synchronous apparatus which can satisfy the need described above.
It is another and more specific object of the present invention to provide a dependent synchronization apparatus which can facilitate implementation of a network, can eliminate erroneous setting of timing sources, and can allow a direction of a timing dependency to be easily checked even after an automatic switching of a direction of a timing dependency.
In order to achieve the above objects according to the present invention, an apparatus which depends on one of a plurality of master clocks as a timing source includes a timing-dependency-direction-identifier-extraction unit which detects an identifier indicative of a direction of timing dependency from a received signal with respect to each of the master clocks, a timing-quality-information-extraction unit which detects a code indicative of a timing quality from the received signal with respect to each of the master clocks, and a synchronization unit which selects the timing source based on the code indicative of a timing quality, and identifies a direction of timing dependency of the timing source based on the identifier indicative of a direction of timing dependency.
When the apparatus as described above is used as a network element in a network, a direction of timing dependency can be easily identified with respect to each of the network elements by checking the identifier indicative of a direction of timing dependency detected in each of the network elements. Since a check of a direction of timing dependency is easily made with respect to each network element, speedy implementation of a large network is facilitated, and erroneous setting of timing sources is eliminated.